A D Flip-Flop ( D
standing for Data or Delay ) can be made from a JK Flip-Flop if K is
always the compliment of J. By adding an inverter between the two, this
insures that J = input D and K = the compliment of input D. To simplify
this circuit consider the figure below:
In this representation, the JK Flip-Flop has been
replaced by a square with all of the inputs and outputs of the JK
Flip-Flop symbolized as letters. At this point you may be wondering,
"what does the D Flip-Flop do?..." Primarily it is used as a data
storage unit. It can store a bit of information similar to the RS
Flip-Flop, but with a lot more capabity. Also, the D Flip-Flop can be
cascaded to create shift registers. On the other hand, the D Flip-Flop
can be made to act
like a T Flip-Flop, which is somewhat of a backwards compatibility
advantage, however it lacks some benefits that the JK Flip Flop has,
such as it cannot be put into a non operational state, since the
"internal" J and K inputs are coupled by an inverter. In order to
achieve the "do-nothing" state, J and K both have to be low.
An important, but possibly confusing concept, is the
difference between level and edge clocked systems. Up to this point all
of the flip flops have been level clocked based. They do something
during one state and do something else on a different state.
Unfortantely this seemingly error/glitch proof design has a
considerable disadvantage. It cannot be used to reliably take "random"
inputs from an external source. Imagine you have just built a frequency
counter, dont worry you don't actually have to know how to build one of
these yet, and it displays on its screen the number of pulses that come
into its input per second. These inputs per second (also known as
frequency: measured in Hertz Hz) are essentially random . They
are not synchronyzed with the frequency counter's internal clock. Since
level clocked circuits can only take inputs at certain clock levels,
there is no guarantee that every pulse received will actually be
counted. If the inputs are not counted properly, the accuracy of the
system is lost and it becomes unuseful.
The solution to this problem is to design the
Flip-Flops to be edge clocked. In an edge clocked system, Everything
happens on the edge of the clock.
In the level clocked T Flip-Flop from the previous
was passed into the master stage on one level and then passed to the
slave stage, where it reaches the output, on the other clock level. In
an edge clocked system, the information is
transferred and displayed on the outputs on one particular clock level.
This particular level depends on whether on not the design is positive
or negative edge triggered. For this reason, an edge triggered device
can have its inputs connected to a randomly changing source, but will
only take these inputs in on a certain "edge" of the clock signal. A
level clocked device must have its inputs wither synchronized with the
clock or unchanging to work properly. The concept can be
quite confusing, but will generally become easier to understand as you
become more familiar with the application of flip-flops. The simulation
ahead will deomonstarte the differences between a level clocked D
Flip-Flop and an edge clocked D Flip-Flop.
As a general rule, level clocked systems can be used
to make clocks, counters, and sequencers, whereas edge clocked systems
can be used to make synchronyzers (when accurately taking random data
is important ) as well as the stuff level clocked circuits can
make. It really depends on the application.
Although both level and edge clocked D Flip-Flops
exist, for most applications the edge clocked style would be
preferable. The following schematics are those of the level and
edge clocked D Flip-Flops...
The Negative Level
Clocked D Flip-Flop (using NAND gates), (Shown before at top of
The Negative Edge
Clocked D Flip-Flop (using NAND gates)....